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Download or read book Digital Background Calibration Techniques for Current-steering Digital-to-analog Converters written by Jenny Kuo and published by . This book was released on 2011 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Current-steering (CS) digital-to-analog converters (DACs) are typically used for high-speed, high-accuracy applications since they are the fastest DAC architecture available that also can achieve relatively high resolution and linearity. However, as the performance specifications for both speed and accuracy in data converters continue to increase, circuit nonidealities are becoming more difficult to overcome using traditional analog design techniques. As a result, digital calibration has become an efficient and effective solution for designing high-performance DACs, where the advantages of process scaling can be fully exploited. Two digital background calibration techniques for CS DACs are presented in this thesis. The first technique improves the static linearity of a binary-weighted (BW) DAC by estimating and correcting for errors due to both mismatch and finite output resistance in the current sources, potentially allowing the DAC to be constructed with minimum size current sources. The errors are estimated with a slow-but-accurate reference analog-to-digital converter (Ref ADC) and a digital adaptive least-mean-squared algorithm. Correction is achieved using two auxiliary BW CS DACs: one for coarse correction and one for fine correction. Since the current source array of the DAC under calibration occupies a small area, gradient effects are small; however, these errors also can be overcome with the calibration described in this thesis. The dynamic performance of the DAC also improves with this calibration technique due to the reduced parasitics stemming from the reduced DAC area. Computer simulations demonstrate the effectiveness of the proposed technique for a 14-bit DAC operating at 100 MS/s. The second technique improves the dynamic linearity of a high-speed CS DAC. At high operating frequencies, the parasitic capacitors at the drain of the current sources dominate the finite output impedance of the DAC, causing input-dependent settling and memory errors. These errors introduce undesired frequency-dependent nonlinearities in the DAC output. The presented calibration technique estimates these errors with a slow-but-accurate Ref ADC and a digital adaptive recursive least-mean-squared algorithm. Correction is achieved using an auxiliary CS DAC. Computer simulations demonstrate the effectiveness of the proposed technique for a 12-bit DAC operating at 1 GS/s.